The present invention generally relates to an application specific integrated circuit and specifically to the use of an FPGA interconnect for flexible I/O connectivity.
Today""s ASIC standard cell designs are often I/O limited, that is, the amount of logic that is placed on a chip is often limited by the number of input/output pins available to connect the logic with the outside world. As a result silicon area that could contain additional function is wasted. Using a larger die than necessary for the logical function in order to obtain sufficient input/output pins adds cost to the product without adding value. Chips designed to support multiple applications may contain multiple functions only one of which is used for a particular application. If an on-chip function could be selectively connected to chip input/output pins based on the application using the chip, then the chip could be implemented with fewer I/O than if all functions had to be wired out at all times. In this case both the chip silicon and chip I/O could be fully utilized, eliminating wasted silicon area, and multiple markets could be satisfied by the same chip.
Today chip designers are often forced to go with a larger chip size than required by the logical function in order to obtain the number of I/O pins required by the design. This adds cost to the product without adding any functional value. The additional cost comes from paying for a larger, more expensive chip than required and also through potential yield loss due to fewer chips per wafer.
Providing chips with functions specific to a particular application may today be implemented as multiple separate part numbers, which is less efficient and more costly in terms of design time and inventory than a single configurable part.
Another problem is when a reversed bit ordering wiring errors are made on the printed circuit board when implementing an ASIC. The reversed bus bit ordering on a PCB is a common problem and is usually solved by re-fabbing the board or by adding xe2x80x9cjumper wiresxe2x80x9d to the incorrectly wired board to correct the ordering. These methods are expensive and time consuming and can impact the overall time-to-market of the design.
The pin reconfiguration can also be accomplished within standard cell chips using standard cell registers to control the reconfiguration of the I/O. Using registers for pin reconfiguration can be effective, but does not work in all cases Examples include 1) when the configuration determination needs to be made prior to being able to write into the standard cell registers, or 2) there is no processor in the system that can write configuration information into the registers.
Accordingly, what is needed is a system and method that provides this functionality. The present invention addresses such a need.
An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions.
An ASIC in accordance with the present invention allows xe2x80x9cfield selectionxe2x80x9d of functions that are connected to the internal bus(es) and to external I/O. The functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for additional external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.